Integrated circuits (ICs) and other electronic apparatus often include arrangements of interconnected field effect transistor (FET) devices, also called metal-oxide-semiconductor field effect transistors (MOSFETs), or simply MOS transistors or devices. A control voltage applied to a gate electrode of the FET device controls the flow of current through a controllable conductive channel between source and drain electrodes.
Transistor devices are often designed to be tolerant of the high currents and voltages that are present in applications such as motion control, air bag deployment, and automotive fuel injector drivers. High voltage transistor devices may have a number of features customized to prevent breakdown resulting from the high electric fields arising from such high voltages. The potential for damage from high energy charge carriers increases with the higher operating voltages achieved as a result of the design features. The higher operating voltages lead to higher electric fields, which, in turn, increase the energy imparted to the charge carriers within the device. Device degradation often arises from the injection of high energy charge carriers, or hot carriers, into the gate oxide, an interlayer dielectric, or field oxide structure of the device. The resulting buildup of charge in the dielectrics from such hot carrier injection (HCI) leads to variations in operational characteristics, such as the threshold voltage or on-state current, and performance of the device, such as performance at high frequencies.
High voltage transistor devices are also susceptible to the generation of secondary charge carriers through impact ionization. In an n-channel transistor device, electrons may generate additional electron-hole pairs after being accelerated in a region having a high electric field, such as near the drain boundary. If a sufficient number of holes—the secondary charge carriers—are created to raise the potential of the body of the transistor device to an extent that the junction with the source is forward biased, activation of a parasitic npn bipolar transistor formed via the source (emitter), body (base), and drain (collector) regions of the transistor device can occur. Very large, damaging currents can result via the activation of the parasitic bipolar transistor, an operating condition referred to as “snapback.”
High voltage devices are often characterized by a “safe operating area” (SOA) in which the operating current and voltage levels are below levels that would result in a snapback event. Attempts to remain within the safe operating area to avoid device destruction or other damage are often undesirably limiting factors for device operation and application.
Transistor devices are often merged with one another to achieve area savings. Merging transistor devices typically involves placement of the transistor devices within a common isolation ring. The merged transistor devices may thus share a common body. Unfortunately, conventional mergeable transistor device designs typically exhibit unacceptably HCI degradation and poor SOA. Conversely, many transistor devices designed for HCI immunity and good SOA are not mergeable.